Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

3-634 Vol. 2
INSTRUCTION SET REFERENCE, A-M
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask
Description
Extracts the sign bits from the packed single-precision floating-point values in the
source operand (second operand), formats them into a 4-bit mask, and stores the
mask in the destination operand (first operand). The source operand is an XMM
register, and the destination operand is a general-purpose register. The mask is
stored in the 4 low-order bits of the destination operand.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operands. See the summary chart at the beginning of this
section for encoding data and limits.
Operation
DEST[0] ← SRC[31];
DEST[1] ← SRC[63];
DEST[2] ← SRC[95];
DEST[3] ← SRC[127];
IF DEST = r32
THEN DEST[31:4] ← ZeroExtend;
ELSE DEST[63:4] ← ZeroExtend;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
int_mm_movemask_ps(__m128 a)
SIMD Floating-Point Exceptions
None.
Opcode Instruction
64-Bit
Mode
Compat/
Leg
Mode Description
0F 50 /r MOVMSKPS r32,
xmm
Valid Valid Extract 4-bit sign mask from
xmm and store in r32.
REX.W + 0F 50 /r MOVMSKPS r64,
xmm
Valid N.E. Extract 4-bit sign mask from
xmm and store in r64. Zero
extend 32-bit results to 64-bits.