Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-55
INSTRUCTION SET REFERENCE, A-M
ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-
Point Values
Description
Performs a bitwise logical AND of the two packed double-precision floating-point
values from the source operand (second operand) and the destination operand (first
operand), and stores the result in the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[127:0] ← DEST[127:0] BitwiseAND SRC[127:0];
Intel C/C++ Compiler Intrinsic Equivalent
ANDPD __m128d _mm_and_pd(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
66 0F 54
/r
ANDPD xmm1,
xmm2/m128
Valid Valid Bitwise logical AND of xmm2/m128
and xmm1.