Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-23
PROTECTED-MODE MEMORY MANAGEMENT
To minimize the number of bus cycles required for address translation, the most
recently accessed page-directory and page-table entries are cached in the processor
in devices called translation lookaside buffers (TLBs). The TLBs satisfy most requests
for reading the current page directory and page tables without requiring a bus cycle.
Extra bus cycles occur only when the TLBs do not contain a page-table entry, which
typically happens when a page has not been accessed for a long time. See Section
3.12, “Translation Lookaside Buffers (TLBs)”, for more information on the TLBs.
3.6.1 Paging Options
Paging is controlled by three flags in the processor’s control registers:
• PG (paging) flag. Bit 31 of CR0 (available in all IA-32 processors beginning with
the Intel386 processor).
• PSE (page size extensions) flag. Bit 4 of CR4 (introduced in the Pentium
processor).
• PAE (physical address extension) flag. Bit 5 of CR4 (introduced in the
Pentium Pro processors).
The PG flag enables the page-translation mechanism. The operating system or exec-
utive usually sets this flag during processor initialization. The PG flag must be set if
the processor’s page-translation mechanism is to be used to implement a demand-
paged virtual memory system or if the operating system is designed to run more
than one program (or task) in virtual-8086 mode.
The PSE flag enables large page sizes: 4-MByte pages or 2-MByte pages (when the
PAE flag is set). When the PSE flag is clear, the more common page length of 4
KBytes is used. See Section 3.7.2, “Linear Address Translation (4-MByte Pages)”,
Section 3.8.3, “Linear Address Translation With PAE Enabled (2-MByte Pages)”, and
Section 3.9, “36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” for
more information about the use of the PSE flag.
The PAE flag provides a method of extending physical addresses to 36 bits. This phys-
ical address extension can only be used when paging is enabled. It relies on an addi-
tional page directory pointer table that is used along with page directories and page
tables to reference physical addresses above FFFFFFFFH. See Section 3.8, “36-Bit
Physical Addressing Using the PAE Paging Mechanism”, for more information about
extending physical addresses using the PAE flag.
When PAE flag is enabled for Intel 64 processors, the PAE mechanism is enhanced to
support more than 36 bits of physical addressing (if the processor’s implementation
supports more than 36 bits of physical addressing). This applies to IA-32e mode
address translation (see Section 3.10, “PAE-Enabled Paging in IA-32e Mode”) and
enhanced legacy PAE-enabled address translation (see Section 3.8.1, “Enhanced
Legacy PAE Paging”).
The 36-bit page size extension (PSE-36) feature provides an alternate method of
extending physical addressing to 36 bits. This paging mechanism uses the page size
extension mode (enabled with the PSE flag) and modified page directory entries to