Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-24 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
reference physical addresses above FFFFFFFFH. The PSE-36 feature flag (bit 17 in the
EDX register when the CPUID instruction is executed with a source operand of 1)
indicates the availability of this addressing mechanism. See Section 3.9, “36-Bit
Physical Addressing Using the PSE-36 Paging Mechanism”, for more information
about the PSE-36 physical address extension and page size extension mechanism.
3.6.2 Page Tables and Directories in the Absence of Intel
®
64
Technology
The information that the processor uses to translate linear addresses into physical
addresses (when paging is enabled) is contained in four data structures:
• Page directory — An array of 32-bit page-directory entries (PDEs) contained in
a 4-KByte page. Up to 1024 page-directory entries can be held in a page
directory.
• Page table — An array of 32-bit page-table entries (PTEs) contained in a
4-KByte page. Up to 1024 page-table entries can be held in a page table. (Page
tables are not used for 2-MByte or 4-MByte pages. These page sizes are mapped
directly from one or more page-directory entries.)
• Page — A 4-KByte, 2-MByte, or 4-MByte flat address space.
• Page-Directory-Pointer Table — An array of four 64-bit entries, each of which
points to a page directory. This data structure is only used when the physical
address extension is enabled (see Section 3.8, “36-Bit Physical Addressing Using
the PAE Paging Mechanism”).
These tables provide access to either 4-KByte or 4-MByte pages when normal 32-bit
physical addressing is being used and to either 4-KByte or 2-MByte pages or 4-MByte
pages only when extended (36-bit) physical addressing is being used.
Table 3-3 shows the page size and physical address size obtained from various
settings of the paging control flags and the PSE-36 CPUID feature flag. Each page-
directory entry contains a PS (page size) flag that specifies whether the entry points
to a page table whose entries in turn point to 4-KByte pages (PS set to 0) or whether
the page-directory entry points directly to a 4-MByte (PSE and PS set to 1) or
2-MByte page (PAE and PS set to 1).
3.7 PAGE TRANSLATION USING 32-BIT PHYSICAL
ADDRESSING
The following sections describe the IA-32 architecture’s page translation mechanism
when using 32-bit physical addresses and a maximum physical address space of 4