Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-25
PROTECTED-MODE MEMORY MANAGEMENT
GBytes. The 32-bit physical addressing described applies to IA-32 processors or when
the following situations are all true:
• The processor supports Intel 64 architecture but IA-32e mode is not active.
• PAE or PSE mechanism is not active.
Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism” and
Section 3.9, “36-Bit Physical Addressing Using the PSE-36 Paging Mechanism”
describe extensions to this page translation mechanism to support 36-bit physical
addresses and a maximum physical address space of 64 GBytes.
3.7.1 Linear Address Translation (4-KByte Pages)
Figure 3-12 shows the page directory and page-table hierarchy when mapping linear
addresses to 4-KByte pages. The entries in the page directory point to page tables,
and the entries in a page table point to pages in physical memory. This paging
method can be used to address up to 2
20
pages, which spans a linear address space
of 2
32
bytes (4 GBytes).
Table 3-3. Page Sizes and Physical Address Sizes
PG Flag,
CR0
PAE Flag,
CR4
PSE Flag,
CR4
PS Flag,
PDE
PSE-36 CPUID
Feature Flag Page Size
Physical Address
Size
0 X X X X — Paging Disabled
1 0 0 X X 4 KBytes 32 Bits
1 0 1 0 X 4 KBytes 32 Bits
10 11 04 MBytes32 Bits
10 11 14 MBytes36 Bits
1 1 X 0 X 4 KBytes 36 Bits
11 X1 X2 MBytes36 Bits