Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-26 Vol. 3A

PROTECTED-MODE MEMORY MANAGEMENT

To select the various table entries, the linear address is divided into three sections:

• Page-directory entry — Bits 22 through 31 provide an offset to an entry in the

page directory. The selected entry provides the base physical address of a page

table.

• Page-table entry — Bits 12 through 21 of the linear address provide an offset to

an entry in the selected page table. This entry provides the base physical address

of a page in physical memory.

• Page offset — Bits 0 through 11 provides an offset to a physical address in the

page.

Memory management software has the option of using one page directory for all

programs and tasks, one page directory for each task, or some combination of the

two.

3.7.2 Linear Address Translation (4-MByte Pages)

Figure 3-13 shows how a page directory can be used to map linear addresses to

4-MByte pages. The entries in the page directory point to 4-MByte pages in physical

memory. This paging method can be used to map up to 1024 pages into a 4-GByte

linear address space.

Figure 3-12. Linear Address Translation (4-KByte Pages)