Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-27
PROTECTED-MODE MEMORY MANAGEMENT
The 4-MByte page size is selected by setting the PSE flag in control register CR4 and
setting the page size (PS) flag in a page-directory entry (see Figure 3-14). With
these flags set, the linear address is divided into two sections:
• Page directory entry—Bits 22 through 31 provide an offset to an entry in the page
directory. The selected entry provides the base physical address of a 4-MByte
page.
• Page offset—Bits 0 through 21 provides an offset to a physical address in the
page.
NOTE
(For the Pentium processor only.) When enabling or disabling large
page sizes, the TLBs must be invalidated (flushed) after the PSE flag
in control register CR4 has been set or cleared. Otherwise, incorrect
page translation might occur due to the processor using outdated
page translation information stored in the TLBs. See Section 10.9,
“Invalidating the Translation Lookaside Buffers (TLBs)”, for
information on how to invalidate the TLBs.
3.7.3 Mixing 4-KByte and 4-MByte Pages
When the PSE flag in CR4 is set, both 4-MByte pages and page tables for 4-KByte
pages can be accessed from the same page directory. If the PSE flag is clear, only
page tables for 4-KByte pages can be accessed (regardless of the setting of the PS
flag in a page-directory entry).
Figure 3-13. Linear Address Translation (4-MByte Pages)
0
Directory
Offset
Page Directory
Directory Entry
CR3 (PDBR)
4-MByte Page
Physical Address
31 2122
Linear Address
1024 PDE = 1024 Pages
10
22
32*
*32 bits aligned onto a 4-KByte boundary.
10