Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-28 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
A typical example of mixing 4-KByte and 4-MByte pages is to place the operating
system or executive’s kernel in a large page to reduce TLB misses and thus improve
overall system performance.
The processor maintains 4-MByte page entries and 4-KByte page entries in separate
TLBs. So, placing often used code such as the kernel in a large page, frees up
4-KByte-page TLB entries for application programs and tasks.
3.7.4 Memory Aliasing
The IA-32 architecture permits memory aliasing by allowing two page-directory
entries to point to a common page-table entry. Software that needs to implement
memory aliasing in this manner must manage the consistency of the accessed and
dirty bits in the page-directory and page-table entries. Allowing the accessed and
dirty bits for the two page-directory entries to become inconsistent may lead to a
processor deadlock.
3.7.5 Base Address of the Page Directory
The physical address of the current page directory is stored in the CR3 register (also
called the page directory base register or PDBR). (See Figure 2-6 and Section 2.5,
“Control Registers”, for more information on the PDBR.) If paging is to be used, the
PDBR must be loaded as part of the processor initialization process (prior to enabling
paging). The PDBR can then be changed either explicitly by loading a new value in
CR3 with a MOV instruction or implicitly as part of a task switch. (See Section 6.2.1,
“Task-State Segment (TSS)”, for a description of how the contents of the CR3
register is set for a task.)
There is no present flag in the PDBR for the page directory. The page directory may
be not-present (paged out of physical memory) while its associated task is
suspended, but the operating system must ensure that the page directory indicated
by the PDBR image in a task's TSS is present in physical memory before the task is
dispatched. The page directory must also remain in memory as long as the task is
active.
3.7.6 Page-Directory and Page-Table Entries
Figure 3-14 shows the format for the page-directory and page-table entries when
4-KByte pages and 32-bit physical addresses are being used. Figure 3-15 shows
the format for the page-directory entries when 4-MByte pages and 32-bit physical
addresses are being used. The functions of the flags and fields in the entries in
Figures 3-14 and 3-15 are as follows:
Page base address, bits 12 through 32
(Page-table entries for 4-KByte pages) — Specifies the physical
address of the first byte of a 4-KByte page. The bits in this field are