Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-29
PROTECTED-MODE MEMORY MANAGEMENT
interpreted as the 20 most-significant bits of the physical address,
which forces pages to be aligned on 4-KByte boundaries.
(Page-directory entries for 4-KByte page tables) — Specifies the
physical address of the first byte of a page table. The bits in this field
are interpreted as the 20 most-significant bits of the physical address,
which forces page tables to be aligned on 4-KByte boundaries.
(Page-directory entries for 4-MByte pages) — Specifies the physical
address of the first byte of a 4-MByte page. Only bits 22 through 31 of
this field are used (and bits 12 through 21 are reserved and must be
set to 0, for IA-32 processors through the Pentium II processor). The
Figure 3-14. Format of Page-Directory and Page-Table Entries for 4-KByte Pages
and 32-Bit Physical Addresses
31
Available for system programmer’s use
Global page (Ignored)
Page size (0 indicates 4 KBytes)
Reserved (set to 0)
12
11
9
8
7
6
543
2
1
0
P
S
P
CA0
Accessed
Cache disabled
Write-through
User/Supervisor
Read/Write
Present
D
P
P
W
T
U
/
S
R
/
W
GAvailPage-Table Base Address
31
Available for system programmer’s use
Global Page
Page Table Attribute Index
Dirty
12
11
9
8
7
6
543
2
1
0
P
CAD
Accessed
Cache Disabled
Write-Through
User/Supervisor
Read/Write
Present
D
P
P
W
T
U
/
S
R
/
W
AvailPage Base Address
Page-Directory Entry (4-KByte Page Table)
Page-Table Entry (4-KByte Page)
P
A
T
G