Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-30 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
base address bits are interpreted as the 10 most-significant bits of the
physical address, which forces 4-MByte pages to be aligned on
4-MByte boundaries.
Present (P) flag, bit 0
Indicates whether the page or page table being pointed to by the
entry is currently loaded in physical memory. When the flag is set, the
page is in physical memory and address translation is carried out.
When the flag is clear, the page is not in memory and, if the processor
attempts to access the page, it generates a page-fault exception
(#PF).
The processor does not set or clear this flag; it is up to the operating
system or executive to maintain the state of the flag.
If the processor generates a page-fault exception, the operating
system generally needs to carry out the following operations:
1. Copy the page from disk storage into physical memory.
2. Load the page address into the page-table or page-directory
entry and set its present flag. Other flags, such as the dirty and
accessed flags, may also be set at this time.
3. Invalidate the current page-table entry in the TLB (see Section
3.12, “Translation Lookaside Buffers (TLBs)”, for a discussion of
TLBs and how to invalidate them).
4. Return from the page-fault handler to restart the interrupted
program (or task).
Figure 3-15. Format of Page-Directory Entries for 4-MByte Pages and 32-Bit
Addresses
31
Available for system programmer’s use
Global page
Page size (1 indicates 4 MBytes)
Dirty
12
11
9
8
7
6
543
2
1
0
P
S
P
CAD
Accessed
Cache disabled
Write-through
User/Supervisor
Read/Write
Present
D
P
P
W
T
U
/
S
R
/
W
G
Avail.Page Base Address
Page-Directory Entry (4-MByte Page)
22
21
Reserved
Page Table Attribute Index
P
A
T
13