Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-32 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
to manage the transfer of pages and page tables into and out of phys-
ical memory.
NOTE: The accesses used by the processor to set this bit may or may
not be exposed to the processor’s Self-Modifying Code detection logic.
If the processor is executing code from the same memory area that is
being used for page table structures, the setting of the bit may or may
not result in an immediate change to the executing code stream.
Dirty (D) flag, bit 6
Indicates whether a page has been written to when set. (This flag is
not used in page-directory entries that point to page tables.) Memory
management software typically clears this flag when a page is initially
loaded into physical memory. The processor then sets this flag the
first time a page is accessed for a write operation.
This flag is “sticky,” meaning that once set, the processor does not
implicitly clear it. Only software can clear this flag. The dirty and
accessed flags are provided for use by memory management software
to manage the transfer of pages and page tables into and out of phys-
ical memory.
NOTE: The accesses used by the processor to set this bit may or may
not be exposed to the processor’s Self-Modifying Code detection logic.
If the processor is executing code from the same memory area that is
being used for page table structures, the setting of the bit may or may
not result in an immediate change to the executing code stream.
Page size (PS) flag, bit 7 page-directory entries for 4-KByte pages
Determines the page size. When this flag is clear, the page size is 4
KBytes and the page-directory entry points to a page table. When the
flag is set, the page size is 4 MBytes for normal 32-bit addressing (and
2 MBytes if extended physical addressing is enabled) and the page-
directory entry points to a page. If the page-directory entry points to
a page table, all the pages associated with that page table will be
4-KByte pages.
Page attribute table index (PAT) flag, bit 7 in page-table entries for
4-KByte pages and bit 12 in page-directory entries for
4-MByte pages
(Introduced in the Pentium III processor) — Selects PAT entry. For
processors that support the page attribute table (PAT), this flag is
used along with the PCD and PWT flags to select an entry in the PAT,
which in turn selects the memory type for the page (see Section
10.12, “Page Attribute Table (PAT)”). For processors that do not
support the PAT, this bit is reserved and should be set to 0.
Global (G) flag, bit 8
(Introduced in the Pentium Pro processor) — Indicates a global page
when set. When a page is marked global and the page global enable
(PGE) flag in register CR4 is set, the page-table or page-directory