Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-33
PROTECTED-MODE MEMORY MANAGEMENT
entry for the page is not invalidated in the TLB when register CR3 is
loaded or a task switch occurs. This flag is provided to prevent
frequently used pages (such as pages that contain kernel or other
operating system or executive code) from being flushed from the
TLB. Only software can set or clear this flag. For page-directory
entries that point to page tables, this flag is ignored and the global
characteristics of a page are set in the page-table entries. See
Section 3.12, “Translation Lookaside Buffers (TLBs)”, for more infor-
mation about the use of this flag. (This bit is reserved in Pentium and
earlier IA-32 processors.)
Reserved and available-to-software bits
For all IA-32 processors. Bits 9, 10, and 11 are available for use by
software. (When the present bit is clear, bits 1 through 31 are avail-
able to software, see Figure 3-16.) In a page-directory entry that
points to a page table, bit 6 is reserved and should be set to 0. When
the PSE and PAE flags in control register CR4 are set, the processor
generates a page fault if reserved bits are not set to 0.
For Pentium II and earlier processors. Bit 7 in a page-table entry is
reserved and should be set to 0. For a page-directory entry for a
4-MByte page, bits 12 through 21 are reserved and must be set to 0.
For Pentium III and later processors. For a page-directory entry for a
4-MByte page, bits 13 through 21 are reserved and must be set to 0.
3.7.7 Not Present Page-Directory and Page-Table Entries
When the present flag is clear for a page-table or page-directory entry, the operating
system or executive may use the rest of the entry for storage of information such as
the location of the page in the disk storage system (see Figure 3-16).
3.8 36-BIT PHYSICAL ADDRESSING USING THE PAE
PAGING MECHANISM
The PAE paging mechanism and support for 36-bit physical addressing were intro-
duced into the IA-32 architecture in the Pentium Pro processors. Implementation of
this feature in an IA-32 processor is indicated with CPUID feature flag PAE (bit 6 in
the EDX register when the source operand for the CPUID instruction is 2). The phys-
ical address extension (PAE) flag in register CR4 enables the PAE mechanism and
extends physical addresses from 32 bits to 36 bits. Here, the processor provides 4
Figure 3-16. Format of a Page-Table or Page-Directory Entry for a Not-Present Page
31
0
0Available to Operating System or Executive