Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-35
PROTECTED-MODE MEMORY MANAGEMENT
3.8.2 Linear Address Translation With PAE Enabled (4-KByte
Pages)
Figure 3-18 shows the page-directory-pointer, page-directory, and page-table hier-
archy when mapping linear addresses to 4-KByte pages when the PAE paging mech-
anism enabled. This paging method can be used to address up to 2
20
pages, which
spans a linear address space of 2
32
bytes (4 GBytes).
To select the various table entries, the linear address is divided into three sections:
• Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to one of the
4 entries in the page-directory-pointer table. The selected entry provides the
base physical address of a page directory.
• Page-directory entry—Bits 21 through 29 provide an offset to an entry in the
selected page directory. The selected entry provides the base physical address of
a page table.
• Page-table entry—Bits 12 through 20 provide an offset to an entry in the selected
page table. This entry provides the base physical address of a page in physical
memory.
• Page offset—Bits 0 through 11 provide an offset to a physical address in the
page.
Figure 3-18. Linear Address Translation With PAE Enabled (4-KByte Pages)
0
Directory
Table
Offset
Page Directory
Directory Entry
Page Table
Page-Table Entry
4-KByte Page
Physical Address
31 20 111221
Linear Address
Page-Directory-
Dir. Pointer Entry
CR3 (PDPTR)
30 29
Pointer Table
Directory Pointer
4 PDPTE ∗ 512 PDE ∗ 512 PTE = 2
20
Pages
2
9
32*
12
9
*32 bits aligned onto a 32-byte boundary
24