Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-36 Vol. 3A

PROTECTED-MODE MEMORY MANAGEMENT

3.8.3 Linear Address Translation With PAE Enabled (2-MByte

Pages)

Figure 3-19 shows how a page-directory-pointer table and page directories can be

used to map linear addresses to 2-MByte pages when the PAE paging mechanism

enabled. This paging method can be used to map up to 2048 pages (4 page-direc-

tory-pointer-table entries times 512 page-directory entries) into a 4-GByte linear

address space.

When PAE is enabled, the 2-MByte page size is selected by setting the page size (PS)

flag in a page-directory entry (see Figure 3-14). (As shown in Table 3-3, the PSE flag

in control register CR4 has no affect on the page size when PAE is enabled.) With the

PS flag set, the linear address is divided into three sections:

• Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to an entry

in the page-directory-pointer table. The selected entry provides the base physical

address of a page directory.

• Page-directory entry—Bits 21 through 29 provide an offset to an entry in the

page directory. The selected entry provides the base physical address of a

2-MByte page.

• Page offset—Bits 0 through 20 provides an offset to a physical address in the

page.

Figure 3-19. Linear Address Translation With PAE Enabled (2-MByte Pages)