Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-37
PROTECTED-MODE MEMORY MANAGEMENT
3.8.4 Accessing the Full Extended Physical Address Space With
the Extended Page-Table Structure
The page-table structure described in the previous two sections allows up to
4 GBytes of the 64 GByte extended physical address space to be addressed at one
time. Additional 4-GByte sections of physical memory can be addressed in either of
two way:
• Change the pointer in register CR3 to point to another page-directory-pointer
table, which in turn points to another set of page directories and page tables.
• Change entries in the page-directory-pointer table to point to other page direc-
tories, which in turn point to other sets of page tables.
3.8.5 Page-Directory and Page-Table Entries With Extended
Addressing Enabled
Figure 3-20 shows the format for the page-directory-pointer-table, page-direc-
tory, and page-table entries when 4-KByte pages and 36-bit extended physical
addresses are being used. Figure 3-21 shows the format for the page-directory-
pointer-table and page-directory entries when 2-MByte pages and 36-bit extended
physical addresses are being used. The functions of the flags in these entries are the
same as described in Section 3.7.6, “Page-Directory and Page-Table Entries”. The
major differences in these entries are as follows:
• A page-directory-pointer-table entry is added.
• The size of the entries are increased from 32 bits to 64 bits.
• The maximum number of entries in a page directory or page table is 512.
• The base physical address field in each entry is extended to 24 bits.
NOTE
Older IA-32 processors that implement the PAE mechanism use
uncached accesses when loading page-directory-pointer table
entries. This behavior is model specific and not architectural. More
recent Intel 64 and IA-32 processors may cache page-directory-
pointer table entries.