Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-41
PROTECTED-MODE MEMORY MANAGEMENT
Figure 3-22 shows how the expanded page directory entry can be used to map a
32-bit linear address to a 36-bit physical address. Here, the linear address is divided
into two sections:
• Page directory entry — Bits 22 through 35 provide an offset to an entry in the
page directory. The selected entry provides the 14 most significant bits of a
36-bit address, which locates the base physical address of a 4-MByte page.
• Page offset — Bits 0 through 21 provides an offset to a physical address in the
page.
This paging method can be used to map up to 1024 pages into a 64-GByte physical
address space.
Figure 3-23 shows the format for the page-directory entries when 4-MByte pages
and 36-bit physical addresses are being used. Section 3.7.6, “Page-Directory and
Page-Table Entries” describes the functions of the flags and fields in bits 0
through 11.
Figure 3-22. Linear Address Translation (4-MByte Pages)
0
Directory
Offset
Page Directory
Directory Entry
CR3 (PDBR)
4-MByte Page
Physical Address
31 2122
Linear Address
1024 PDE = 1024 Pages
10
22
32*
*32 bits aligned onto a 4-KByte boundary.
14