Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1
3-42 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
3.10 PAE-ENABLED PAGING IN IA-32E MODE
Intel 64 architecture expands physical address extension (PAE) paging structures to
potentially support mapping a 64-bit linear address to a 52-bit physical address. In
the first implementation of Intel 64 architecture, PAE paging structures support
translation of a 48-bit linear address into a 40-bit physical address.
When IA-32e mode is enabled, linear address to physical address translation is
different than in PAE-enabled protected mode. Address translation from a linear
address to a physical address uses up to four levels of paging data structures. A new
page mapping table, the page map level 4 table (PML4 table), is added on top of the
page director pointer table.
Prior to activating IA-32e mode, PAE must be enabled by setting CR4.PAE = 1. PAE
expands the size of page-directory entries (PDE) and page-table entries (PTE) from
32 bits to 64 bits. This change is made to support physical-address sizes of greater
than 32 bits. An attempt to activate IA-32e mode prior to enabling PAE results in a
general-protection exception, #GP.
PML4 tables are used in page translation only in IA-32e mode. They are not used
when IA-32e mode is disabled, whether or not PAE is enabled. The existing page-
directory pointer table is expanded to 512 eight-byte entries from four entries. As a
result, nine bits of the linear address are used to index into a PDP table rather than
two bits. The size of the page-directory entry (PDE) table and page-table entry (PTE)
table remains 512 eight-byte entries, each indexed by nine linear-address bits. The
total of linear-address index bits into the collection of paging data structures (PML4
Figure 3-23. Format of Page-Directory Entries for 4-MByte Pages and
36-Bit Physical Addresses
31
Available for system programmer’s use
Global page
Page size (must be set to 1)
Dirty
12
11 9
8
7
6
543
2
10
P
S
P
C
AD
Accessed
Cache disabled
Write-through
User/Supervisor
Read/Write
Present
D
P
P
W
T
U
/
S
R
/
W
GAvail.
Page Base Address
Page-Directory Entry (4-MByte Page)
22
21
Reserved
13
16
(Bits 22 Through 31)
Page Base Address (Bits 32 Through 35)
Page Attribute Table Index
17
P
A
T