Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-43
PROTECTED-MODE MEMORY MANAGEMENT
+ PDP + PDE + PTE + page offset) becomes 48. The method for translating the high-
order 16 linear-address bits into a physical address is currently reserved.
The PS flag in the page directory entry (PDE.PS) selects between 4-KByte and
2-MByte page sizes. Because PDE.PS is used to control large page selection, the
CR4.PSE bit is ignored.
3.10.1 IA-32e Mode Linear Address Translation (4-KByte Pages)
Figure 3-24 shows the PML4, page-directory-pointer, page-directory, and page-table
hierarchy when mapping linear addresses to 4-KByte pages in IA-32e mode. This
paging method can be used to address up to 2
36
pages, which spans a linear address
space of 2
48
bytes.
To select the various table entries, linear addresses are divided into five sections:
• PML4-table entry — Bits 47:39 provide an offset to an entry in the PML4 table.
The selected entry provides the base physical address of a page directory pointer
table.
• Page-directory-pointer-table entry — Bits 38:30 provide an offset to an
entry in the page-directory-pointer table. The selected entry provides the base
physical address of a page directory table.
• Page-directory entry — Bits 29:21 provide an offset to an entry in the selected
page directory. The selected entry provides the base physical address of a page
table.
• Page-table entry — Bits 20:12 provide an offset to an entry in the selected
page table. This entry provides the base physical address of a page in physical
memory.
• Page offset — Bits 11:0 provide an offset to a physical address in the page.