Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-46 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
Except for the PML4 table; enhanced formats of page-directory-pointer table, page-
directory, and page-table entries are also used in enhanced legacy PAE-enabled
paging on processors that support Intel 64 architecture (see Section 3.8.1,
“Enhanced Legacy PAE Paging”).
Except for bit 63, functions of the flags in these entries are as described in Section
3.7.6, “Page-Directory and Page-Table Entries”. The differences are:
• A PML4 table entry and a page-directory-pointer-table entry are added.
• Entries are increased from 32 bits to 64 bits.
Figure 3-26. Format of Paging Structure Entries for 4-KByte Pages in IA-32e Mode
63
32
Reserved (set to 0)
Page-Directory-Pointer-Table Entry
31
12
11
9
8
543
2
0
P
C
D
P
W
T
Avail Page-Directory Base Address
Rsvd
63
32
Reserved (set to 0)
Page-Directory Entry (4-KByte Page Table)
31
12
11
9
876
543
2
1
0
P
C
0
D
P
P
W
T
Page-Table Base Address
00 A
R
/
W
U
/
S
63
32
Reserved (set to 0)
Page-Table Entry (4-KByte Page)
31
12
11
9
8
7
6
543
2
1
0
P
C
D
D
P
P
W
T
Page Base Address
GA
R
/
W
U
/
S
Avail
Avail
P
1
P
A
T
63
32
Base Address
Reserved (set to 0)
Page-Map-Level-4-Table Entry
31
12
11
9
8
543
2
0
P
C
D
P
W
T
Avail
PML4 Base Address
Rsvd.
P
1
3962
Avail
E
X
B
51
3962
Avail
E
X
B
51
3962
Avail
E
X
B
51
R
/
W
U
/
S
3962
Avail
E
X
B
51
6
A
6
A
R
/
W
U
/
S
Base Address
Base Address
Base Address