Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

3-48 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
3.10.3.1 Intel
®
64 Processors and Reserved Bit Checking
On processors supporting Intel 64 architecture and/or supporting the execute disable
bit, the processor enforces reserved bit checking on paging mode specific bits.
Table 3-4 shows the reserved bits that are checked on Intel 64 processors when
execute disable bit checking is either disabled or not supported. The 32-bit mode
behavior in Table 3-4 also applies to IA-32 processors that support the execute-
disable bit but not Intel 64 architecture.
If the execute disable bit is enabled in an IA-32 or Intel 64 processor, reserved bits
in paging data structures for legacy 32-bit mode and 64-bit mode are shown in
Table 3-5.
Table 3-4. Reserved Bit Checking When Execute Disable Bit is Disabled
Mode Paging Mode Paging Structure Check Bits
32-bit 4-KByte pages (PAE = 0, PSE = 0) PDE and PT No reserved bits checked
4-MByte page (PAE = 0, PSE = 1) PDE Bit [21]
4-KByte page (PAE = 0, PSE = 1) PDE No reserved bits checked
4-KByte and 4-MByte page (PAE = 0,
PSE = 1)
PTE No reserved bits checked
4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PDP table entry Bits [63:40] & [8:5] & [2:1]
2-MByte page (PAE = 1, PSE = x) PDE Bits [63:40] & [20:13]
4-KByte pages (PAE =1, PSE = x) PDE Bits [63:40]
4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PTE Bits [63:40]
64-bit 4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PML4E Bit [63], bits [51:40]
4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PDPTE Bit [63], bits [51:40]
2-MByte page (PAE =1, PSE = x) PDE, 2-MByte page Bit [63], bits [51:40] & [20:13]
4-KByte pages (PAE = 1, PSE = x) PDE, 4-KByte page Bit [63], bits [51:40]
4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PTE Bit [63], bits [51:40]