Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 3-49
PROTECTED-MODE MEMORY MANAGEMENT
3.11 MAPPING SEGMENTS TO PAGES
The segmentation and paging mechanisms provide in the IA-32 architecture support
a wide variety of approaches to memory management. When segmentation and
paging is combined, segments can be mapped to pages in several ways. To imple-
ment a flat (unsegmented) addressing environment, for example, all the code, data,
and stack modules can be mapped to one or more large segments (up to 4-GBytes)
that share same range of linear addresses (see Figure 3-2). Here, segments are
essentially invisible to applications and the operating-system or executive. If paging
is used, the paging mechanism can map a single linear address space (contained in a
single segment) into virtual memory. Or, each program (or task) can have its own
large linear address space (contained in its own segment), which is mapped into
virtual memory through its own page directory and set of page tables.
Segments can be smaller than the size of a page. If one of these segments is placed
in a page which is not shared with another segment, the extra memory is wasted. For
example, a small data structure, such as a 1-byte semaphore, occupies 4K bytes if it
is placed in a page by itself. If many semaphores are used, it is more efficient to pack
them into a single page.
Table 3-5. Reserved Bit Checking When Execute Disable Bit is Enabled
Mode Paging Mode Paging Structure Check Bits
32-bit 4-KByte pages (PAE = 0, PSE = 0) PDE and PT No reserved bits checked
4-MByte page (PAE = 0, PSE = 1) PDE Bit [21]
4-KByte page (PAE = 0, PSE = 1) PDE No reserved bits checked
4-KByte and 4-MByte page (PAE =
0, PSE = 1)
PTE No reserved bits checked
4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PDP table entry Bits [63:40] & [8:5] & [2:1]
2-MByte page (PAE = 1, PSE = x) PDE Bits [62:40] & [20:13]
4-KByte pages (PAE = 1, PSE = x) PDE Bits [62:40]
4-KByte pages (PAE = 1, PSE = x) PTE Bits [62:40]
64-bit 4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PML4E Bits [51:40]
4-KByte and 2-MByte pages (PAE =
1, PSE = x)
PDPTE Bits [51:40]
2-MByte page (PAE = 1, PSE = x) PDE, 2-MByte page Bits [51:40] & [20:13]
4-KByte pages (PAE = 1, PSE = x) PDE, 4-KByte page Bits [51:40]
4-KByte pages (PAE = 1, PSE = x) PTE Bits [51:40]
NOTE:
x = Bit does not impact behavior.