Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

4-34 Vol. 3A
PROTECTION
4.9 PRIVILEGED INSTRUCTIONS
Some of the system instructions (called “privileged instructions”) are protected from
use by application programs. The privileged instructions control system functions
(such as the loading of system registers). They can be executed only when the CPL is
0 (most privileged). If one of these instructions is executed when the CPL is not 0, a
general-protection exception (#GP) is generated. The following system instructions
are privileged instructions:
• LGDT — Load GDT register.
• LLDT — Load LDT register.
• LTR — Load task register.
• LIDT — Load IDT register.
• MOV (control registers) — Load and store control registers.
• LMSW — Load machine status word.
• CLTS — Clear task-switched flag in register CR0.
• MOV (debug registers) — Load and store debug registers.
• INVD — Invalidate cache, without writeback.
• WBINVD — Invalidate cache, with writeback.
• INVLPG —Invalidate TLB entry.
• HLT— Halt processor.
• RDMSR — Read Model-Specific Registers.
• WRMSR —Write Model-Specific Registers.
• RDPMC — Read Performance-Monitoring Counter.
• RDTSC — Read Time-Stamp Counter.
Some of the privileged instructions are available only in the more recent families of
Intel 64 and IA-32 processors (see Section 17.12, “New Instructions In the Pentium
and Later IA-32 Processors”).
The PCE and TSD flags in register CR4 (bits 4 and 2, respectively) enable the RDPMC
and RDTSC instructions, respectively, to be executed at any CPL.
4.10 POINTER VALIDATION
When operating in protected mode, the processor validates all pointers to enforce
protection between segments and maintain isolation between privilege levels.
Pointer validation consists of the following checks:
1. Checking access rights to determine if the segment type is compatible with its
use.
2. Checking read/write rights.