Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

4-44 Vol. 3A

PROTECTION

If the execute disable bit capability is not available, a write to IA32_EFER.NXE

produces a #GP exception. See Table 4-5.

4.13.2 Execute-Disable Bit Page Protection

The execute-disable bit in paging structures enhances page protection for data

pages. Memory pages that contain data cannot be used to execute code if

IA32_EFER.NXE =1 and the execute-disable bit of the memory page is set. Table 4-6

lists the valid usage of a page in relation to the value of execute-disable bit (bit 63)

of the corresponding entry in each level of the paging structures. Execute-disable bit

protection can be activated using the execute-disable bit at any level of the paging

structure, irrespective of the corresponding entry in other levels. When execute-

disable-bit protection is not activated, the page can be used as code or data.

Table 4-5. Extended Feature Enable MSR (IA32_EFER)

63:12 11 10 9 8 7:1 0

Reserved Execute-

disable bit

enable (NXE)

IA-32e mode

active (LMA)

Reserve

IA-32e mode

enable (LME)

Reserve

SysCall enable

(SCE)

Table 4-6. IA-32e Mode Page Level Protection Matrix

with Execute-Disable Bit Capability

Execute Disable Bit Value (Bit 63) Valid Usage

PML4 PDP PDE PTE

Bit 63 = 1 * * * Data

*Bit 63 = 1 * * Data

* * Bit 63 = 1 * Data

* * * Bit 63 = 1 Data

Bit 63 = 0 Bit 63 = 0 Bit 63 = 0 Bit 63 = 0 Data/Code

NOTE:

* Value not checked.