Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 4-45
PROTECTION
In legacy PAE-enabled mode, Table 4-7 and Table 4-8 show the effect of setting the
execute-disable bit for code and data pages.
4.13.3 Reserved Bit Checking
The processor enforces reserved bit checking in paging data structure entries. The
bits being checked varies with paging mode and may vary with the size of physical
address space.
Table 4-9 shows the reserved bits that are checked when the execute disable bit
capability is enabled (CR4.PAE = 1 and IA32_EFER.NXE = 1). Table 4-9 and Table
4-10 show the following paging modes:
• Non-PAE 4-KByte paging: 4-KByte-page only paging (CR4.PAE = 0,
CR4.PSE = 0).
• PSE36: 4-KByte and 4-MByte pages (CR4.PAE = 0, CR4.PSE = 1).
• PAE: 4-KByte and 2-MByte pages (CR4.PAE = 1, CR4.PSE = X).
In legacy PAE-enabled paging, some processors may only support a 36-bit (or
32-bit) physical address size; in such cases reserved bit checking still applies to bits
39:36 (or bits 39:32). See the table note.
Table 4-7. Legacy PAE-Enabled 4-KByte Page Level Protection Matrix
with Execute-Disable Bit Capability
Execute Disable Bit Value (Bit 63) Valid Usage
PDE PTE
Bit 63 = 1 * Data
*Bit 63 = 1Data
Bit 63 = 0 Bit 63 = 0 Data/Code
NOTE:
* Value not checked.
Table 4-8. Legacy PAE-Enabled 2-MByte Page Level Protection
with Execute-Disable Bit Capability
Execute Disable Bit Value (Bit 63) Valid Usage
PDE
Bit 63 = 1 Data
Bit 63 = 0 Data/Code