Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 5-11
INTERRUPT AND EXCEPTION HANDLING
To prevent this situation, the processor inhibits interrupts, debug exceptions, and
single-step trap exceptions after either a MOV to SS instruction or a POP to SS
instruction, until the instruction boundary following the next instruction is reached.
All other faults may still be generated. If the LSS instruction is used to modify the
contents of the SS register (which is the recommended method of modifying this
register), this problem does not occur.
5.9 PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND
INTERRUPTS
If more than one exception or interrupt is pending at an instruction boundary, the
processor services them in a predictable order. Table 5-2 shows the priority among
classes of exception and interrupt sources.
Table 5-2. Priority Among Simultaneous Exceptions and Interrupts
Priority Description
1 (Highest) Hardware Reset and Machine Checks
- RESET
- Machine Check
2Trap on Task Switch
- T flag in TSS is set
3 External Hardware Interventions
- FLUSH
- STOPCLK
- SMI
- INIT
4 Traps on the Previous Instruction
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)
5 Nonmaskable Interrupts (NMI)
1
6 Maskable Hardware Interrupts
1
7 Code Breakpoint Fault
8 Faults from Fetching Next Instruction
- Code-Segment Limit Violation
- Code Page Fault
9Faults from Decoding the Next Instruction
- Instruction length > 15 bytes
- Invalid Opcode
- Coprocessor Not Available