Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 5-13
INTERRUPT AND EXCEPTION HANDLING
The LIDT (load IDT register) and SIDT (store IDT register) instructions load and store
the contents of the IDTR register, respectively. The LIDT instruction loads the IDTR
register with the base address and limit held in a memory operand. This instruction
can be executed only when the CPL is 0. It normally is used by the initialization code
of an operating system when creating an IDT. An operating system also may use it to
change from one IDT to another. The SIDT instruction copies the base and limit value
stored in IDTR to memory. This instruction can be executed at any privilege level.
If a vector references a descriptor beyond the limit of the IDT, a general-protection
exception (#GP) is generated.
NOTE
Because interrupts are delivered to the processor core only once, an
incorrectly configured IDT could result in incomplete interrupt
handling and/or the blocking of interrupt delivery.
IA-32 architecture rules need to be followed for setting up IDTR
base/limit/access fields and each field in the gate descriptors. The
same apply for the Intel 64 architecture. This includes implicit
referencing of the destination code segment through the GDT or LDT
and accessing the stack.
Figure 5-1. Relationship of the IDTR and IDT
IDT Limit
IDT Base Address
+
Interrupt
Descriptor Table (IDT)
Gate for
0
IDTR Register
Interrupt #n
Gate for
Interrupt #3
Gate for
Interrupt #2
Gate for
Interrupt #1
151647
0
31
0
8
16
(n−1)∗8