Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 5-23
INTERRUPT AND EXCEPTION HANDLING
5.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT
MODE
In 64-bit mode, interrupt and exception handling is similar to what has been
described for non-64-bit modes. The following are the exceptions:
• All interrupt handlers pointed by the IDT are in 64-bit code (this does not apply to
the SMI handler).
• The size of interrupt-stack pushes is fixed at 64 bits; and the processor uses
8-byte, zero extended stores.
• The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacy
modes, this push is conditional and based on a change in current privilege level
(CPL).
• The new SS is set to NULL if there is a change in CPL.
• IRET behavior changes.
• There is a new interrupt stack-switch mechanism.
• The alignment of interrupt stack frame is different.
5.14.1 64-Bit Mode IDT
Interrupt and trap gates are 16 bytes in length to provide a 64-bit offset for the
instruction pointer (RIP). The 64-bit RIP referenced by interrupt-gate descriptors
allows an interrupt service routine to be located anywhere in the linear-address
space. See Figure 5-7.