Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A xxvii
CONTENTS
PAGE
Figure 3-6. Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
Figure 3-7. Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Figure 3-8. Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
Figure 3-9. Segment Descriptor When Segment-Present Flag Is Clear. . . . . . . . . . . . . . . . . . . . . .3-15
Figure 3-10. Global and Local Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
Figure 3-11. Pseudo-Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21
Figure 3-12. Linear Address Translation (4-KByte Pages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26
Figure 3-13. Linear Address Translation (4-MByte Pages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27
Figure 3-14. Format of Page-Directory and Page-Table Entries for 4-KByte Pages
and 32-Bit Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-29
Figure 3-15. Format of Page-Directory Entries for 4-MByte Pages and
32-Bit Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-30
Figure 3-16. Format of a Page-Table or Page-Directory Entry for a Not-Present Page . . . . . . .3-33
Figure 3-17. Register CR3 Format When the Physical Address Extension is Enabled . . . . . . . . .3-34
Figure 3-18. Linear Address Translation With PAE Enabled (4-KByte Pages). . . . . . . . . . . . . . . . .3-35
Figure 3-19. Linear Address Translation With PAE Enabled (2-MByte Pages) . . . . . . . . . . . . . . . .3-36
Figure 3-20. Format of Page-Directory-Pointer-Table, Page-Directory, and
Page-Table Entries for 4-KByte Pages with PAE Enabled . . . . . . . . . . . . . . . . . . . . . .3-38
Figure 3-21. Format of Page-Directory-Pointer-Table and Page-Directory Entries
for 2-MByte Pages with PAE Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-39
Figure 3-22. Linear Address Translation (4-MByte Pages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-41
Figure 3-23. Format of Page-Directory Entries for 4-MByte Pages and
36-Bit Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42
Figure 3-24. IA-32e Mode Paging Structures (4-KByte Pages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44
Figure 3-25. IA-32e Mode Paging Structures (2-MByte pages). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45
Figure 3-26. Format of Paging Structure Entries for 4-KByte Pages in IA-32e Mode . . . . . . . . .3-46
Figure 3-27. Format of Paging Structure Entries for 2-MByte Pages in IA-32e Mode. . . . . . . . .3-47
Figure 3-28. Memory Management Convention That Assigns a Page Table
to Each Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-50
Figure 4-1. Descriptor Fields Used for Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-2. Descriptor Fields with Flags used in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-3. Protection Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
Figure 4-4. Privilege Check for Data Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12
Figure 4-5. Examples of Accessing Data Segments From Various Privilege Levels . . . . . . . . . .4-13
Figure 4-6. Privilege Check for Control Transfer Without Using a Gate . . . . . . . . . . . . . . . . . . . . .4-16
Figure 4-7. Examples of Accessing Conforming and Nonconforming Code Segments
From Various Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
Figure 4-8. Call-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19
Figure 4-9. Call-Gate Descriptor in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-21
Figure 4-10. Call-Gate Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22
Figure 4-11. Privilege Check for Control Transfer with Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Figure 4-12. Example of Accessing Call Gates At Various Privilege Levels . . . . . . . . . . . . . . . . . . .4-25
Figure 4-13. Stack Switching During an Interprivilege-Level Call . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-27
Figure 4-14. MSRs Used by SYSCALL and SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-33
Figure 4-15. Use of RPL to Weaken Privilege Level of Called Procedure . . . . . . . . . . . . . . . . . . . . .4-38
Figure 5-1. Relationship of the IDTR and IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
Figure 5-2. IDT Gate Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15
Figure 5-3. Interrupt Procedure Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16
Figure 5-4. Stack Usage on Transfers to Interrupt and Exception-Handling Routines . . . . . . .5-18
Figure 5-5. Interrupt Task Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21
Figure 5-6. Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-22
Figure 5-7. 64-Bit IDT Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24