Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-10 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
respective code sequences are executed on the processors. The final values in loca-
tion A, B, and C would possibly vary on each execution of the write sequence.
The processor-ordering model described in this section is virtually identical to that
used by the Pentium and Intel486 processors. The only enhancements in the Pentium
4, Intel Xeon, and P6 family processors are:
• Added support for speculative reads.
• Store-buffer forwarding, when a read passes a write to the same memory
location.
• Out of order store from long string store and string move operations (see Section
7.2.3, “Out-of-Order Stores For String Operations,” below).
NOTE
In P6 processor family, store-buffer forwarding to reads of WC memory from
streaming stores to the same address does not occur due to errata.
7.2.3 Out-of-Order Stores For String Operations
The Intel Core 2 Duo, Intel Core, Pentium 4, and P6 family processors modify the
processors operation during the string store operations (initiated with the MOVS and
STOS instructions) to maximize performance. Once the “fast string” operations initial
conditions are met (as described below), the processor will essentially operate on,
Figure 7-1. Example of Write Ordering in Multiple-Processor Systems
Processor #1 Processor #2 Processor #3
Write A.3
Write B.3
Write C.3
Write A.1
Write B.1
Write A.2
Write A.3
Write C.1
Write B.2
Write C.2
Write B.3
Write C.3
Order of Writes From Individual Processors
Write A.2
Write B.2
Write C.2
Write A.1
Write B.1
Write C.1
Writes from all
processors are
not guaranteed
to occur in a
particular order.
Each processor
is guaranteed to
perform writes in
program order.
Writes are in order
with respect to
individual processes.
Example of order of actual writes
from all processors to memory