Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-14 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
3. Let all processors invalidate the PTEs and PDEs modified in their TLBs.
4. End barrier — Resume all processors; resume general processing.
Alternate, performance-optimized, TLB shootdown algorithms may be developed;
however, care must be taken by the developers to ensure that either of the following
conditions are met:
• Different TLB mappings are not used on different processors during the update
process.
• The operating system is prepared to deal with the case where processors are
using the stale mapping during the update process.
7.4 SERIALIZING INSTRUCTIONS
The Intel 64 and IA-32 architectures define several serializing instructions. These
instructions force the processor to complete all modifications to flags, registers, and
memory by previous instructions and to drain all buffered writes to memory before
the next instruction is fetched and executed. For example, when a MOV to control
register instruction is used to load a new value into control register CR0 to enable
protected mode, the processor must perform a serializing operation before it enters
protected mode. This serializing operation insures that all operations that were
started while the processor was in real-address mode are completed before the
switch to protected mode is made.
The concept of serializing instructions was introduced into the IA-32 architecture
with the Pentium processor to support parallel instruction execution. Serializing
instructions have no meaning for the Intel486 and earlier processors that do not
implement parallel instruction execution.
It is important to note that executing of serializing instructions on P6 and more
recent processor families constrain speculative execution because the results of
speculatively executed instructions are discarded. The following instructions are seri-
alizing instructions:
• Privileged serializing instructions — MOV (to control register, with the
exception of MOV CR8
1
), MOV (to debug register), WRMSR, INVD, INVLPG,
WBINVD, LGDT, LLDT, LIDT, and LTR.
• Non-privileged serializing instructions — CPUID, IRET, and RSM.
When the processor serializes instruction execution, it ensures that all pending
memory transactions are completed (including writes stored in its store buffer)
before it executes the next
instruction. Nothing can pass a serializing instruction and
a serializing instruction cannot pass any other instruction (read, write, instruction
fetch, or I/O). For example, CPUID can be executed at any privilege level to serialize
instruction execution with no effect on program flow, except that the EAX, EBX, ECX,
and EDX registers are modified.
1. MOV CR8 is not defined architecturally as a serializing instruction.