Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-17
MULTIPLE-PROCESSOR MANAGEMENT
and APs are initialized, the BSP then begins executing the operating-system initial-
ization code.
Following a power-up or reset, the APs complete a minimal self-configuration, then
wait for a startup signal (a SIPI message) from the BSP processor. Upon receiving a
SIPI message, an AP executes the BIOS AP configuration code, which ends with the
AP being placed in halt state.
For Intel 64 and IA-32 processors supporting Hyper-Threading Technology, the MP
initialization protocol treats each of the logical processors on the system bus as a
separate processor (with a unique APIC ID). During boot-up, one of the logical
processors is selected as the BSP and the remainder of the logical processors are
designated as APs.
7.5.2 MP Initialization Protocol Requirements and Restrictions
for Intel Xeon Processors
The MP initialization protocol imposes the following requirements and restrictions on
the system:
• The MP protocol is executed only after a power-up or RESET. If the MP protocol
has completed and a BSP is chosen, subsequent INITs (either to a specific
processor or system wide) do not cause the MP protocol to be repeated. Instead,
each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to
determine whether it should execute the BIOS boot-strap code (if it is the BSP) or
enter a wait-for-SIPI state (if it is an AP).
• All devices in the system that are capable of delivering interrupts to the
processors must be inhibited from doing so for the duration of the MP initial-
ization protocol. The time during which interrupts must be inhibited includes the
window between when the BSP issues an INIT-SIPI-SIPI sequence to an AP and
when the AP responds to the last SIPI in the sequence.
7.5.3 MP Initialization Protocol Algorithm for
Intel Xeon Processors
Following a power-up or RESET of an MP system, the Intel Xeon processors in the
system execute the MP initialization protocol algorithm to initialize each of the logical
processors on the system bus. In the course of executing this algorithm, the
following boot-up and initialization operations are carried out:
1. Each logical processor on the system bus is assigned a unique 8-bit APIC ID,
based on system topology (see Section 7.5.5, “Identifying Logical Processors in
an MP System”). This ID is written into the local APIC ID register for each
processor.
2. Each logical processor is assigned a unique arbitration priority based on its APIC
ID.