Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-18 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
3. Each logical processor executes its internal BIST simultaneously with the other
logical processors on the system bus.
4. Upon completion of the BIST, the logical processors use a hardware-defined
selection mechanism to select the BSP and the APs from the available logical
processors on the system bus. The BSP selection mechanism differs depending
on the family, model, and stepping IDs of the processors, as follows:
— Family, model, and stepping IDs of F0AH and onwards:
• The logical processors begin monitoring the BNR# signal, which is
toggling. When the BNR# pin stops toggling, each processor attempts to
issue a NOP special cycle on the system bus.
• The logical processor with the highest arbitration priority succeeds in
issuing a NOP special cycle and is nominated the BSP. This processor sets
the BSP flag in its IA32_APIC_BASE MSR, then fetches and begins
executing BIOS boot-strap code, beginning at the reset vector (physical
address FFFF FFF0H).
• The remaining logical processors (that failed in issuing a NOP special
cycle) are designated as APs. They leave their BSP flags in the clear state
and enter a “wait-for-SIPI state.”
— Family, model, and stepping IDs up to F09H:
• Each processor broadcasts a BIPI to “all including self.” The first processor
that broadcasts a BIPI (and thus receives its own BIPI vector), selects
itself as the BSP and sets the BSP flag in its IA32_APIC_BASE MSR. (See
Appendix C.1, “Overview of the MP Initialization Process For P6 Family
Processors,” for a description of the BIPI, FIPI, and SIPI messages.)
• The remainder of the processors (which were not selected as the BSP) are
designated as APs. They leave their BSP flags in the clear state and enter
a “wait-for-SIPI state.”
• The newly established BSP broadcasts an FIPI message to “all including
self,” which the BSP and APs treat as an end of MP initialization signal.
Only the processor with its BSP flag set responds to the FIPI message. It
responds by fetching and executing the BIOS boot-strap code, beginning
at the reset vector (physical address FFFF FFF0H).
5. As part of the boot-strap code, the BSP creates an ACPI table and an MP table and
adds its initial APIC ID to these tables as appropriate.
6. At the end of the boot-strap procedure, the BSP sets a processor counter to 1,
then broadcasts a SIPI message to all the APs in the system. Here, the SIPI
message contains a vector to the BIOS AP initialization code (at 000VV000H,
where VV is the vector contained in the SIPI message).
7. The first action of the AP initialization code is to set up a race (among the APs) to
a BIOS initialization semaphore. The first AP to the semaphore begins executing
the initialization code. (See Section 7.5.4, “MP Initialization Example,” for
semaphore implementation details.) As part of the AP initialization procedure,
the AP adds its APIC ID number to the ACPI and MP tables as appropriate and