Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-19
MULTIPLE-PROCESSOR MANAGEMENT
increments the processor counter by 1. At the completion of the initialization
procedure, the AP executes a CLI instruction and halts itself.
8. When each of the APs has gained access to the semaphore and executed the AP
initialization code, the BSP establishes a count for the number of processors
connected to the system bus, completes executing the BIOS boot-strap code,
and then begins executing operating-system boot-strap and start-up code.
9. While the BSP is executing operating-system boot-strap and start-up code, the
APs remain in the halted state. In this state they will respond only to INITs, NMIs,
and SMIs. They will also respond to snoops and to assertions of the STPCLK# pin.
The following section gives an example (with code) of the MP initialization protocol
for multiple Intel Xeon processors operating in an MP configuration.
Appendix B, “Model-Specific Registers (MSRs),” describes how to program the
LINT[0:1] pins of the processor’s local APICs after an MP configuration has been
completed.
7.5.4 MP Initialization Example
The following example illustrates the use of the MP initialization protocol used to
initialize processors in an MP system after the BSP and APs have been established.
The code runs on Intel 64 or IA-32 processors that use a protocol. This includes P6
Family processors, Pentium 4 processors, Intel Core Duo, Intel Core 2 Duo and Intel
Xeon processors.
The following constants and data definitions are used in the accompanying code
examples. They are based on the addresses of the APIC registers defined in Table 8-1.
ICR_LOW EQU 0FEE00300H
SVR EQU 0FEE000F0H
APIC_ID EQU 0FEE00020H
LVT3 EQU 0FEE00370H
APIC_ENABLED EQU 0100H
BOOT_ID DD ?
COUNT EQU 00H
VACANT EQU 00H
7.5.4.1 Typical BSP Initialization Sequence
After the BSP and APs have been selected (by means of a hardware protocol, see
Section 7.5.3, “MP Initialization Protocol Algorithm for Intel Xeon Processors”), the
BSP begins executing BIOS boot-strap code (POST) at the normal IA-32 architecture
starting address (FFFF FFF0H). The boot-strap code typically performs the following
operations:
1. Initializes memory.