Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A xxix
CONTENTS
PAGE
Figure 9-4. Constructing Temporary GDT and Switching to Protected Mode
(Lines 162-172 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-31
Figure 9-5. Moving the GDT, IDT, and TSS from ROM to RAM (Lines 196-261 of
List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-32
Figure 9-6. Task Switching (Lines 282-296 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-33
Figure 9-7. Applying Microcode Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-37
Figure 9-8. Microcode Update Write Operation Flow [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-61
Figure 9-9. Microcode Update Write Operation Flow [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-62
Figure 10-1. Cache Structure of the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . .10-1
Figure 10-2. Cache-Control Registers and Bits Available in IA-32 Processors . . . . . . . . . . . . . . 10-14
Figure 10-3. Mapping Physical Memory With MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
Figure 10-4. IA32_MTRRCAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
Figure 10-5. IA32_MTRR_DEF_TYPE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
Figure 10-6. IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn
Variable-Range Register Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
Figure 10-7. IA32_CR_PAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45
Figure 11-1. Mapping of MMX Registers to Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . .11-2
Figure 11-2. Mapping of MMX Registers to x87 FPU Data Register Stack . . . . . . . . . . . . . . . . . . .11-7
Figure 12-1. Example of Saving the x87 FPU, MMX, SSE, SSE2, SSE3, and SSSE3
State During an Operating-System Controlled Task Switch. . . . . . . . . . . . . . . . . . . 12-10
Figure 13-1. IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination . . . . . . . . . . . . .13-2
Figure 13-2. Processor Modulation Through Stop-Clock Mechanism . . . . . . . . . . . . . . . . . . . . . . . . .13-6
Figure 13-3. MSR_THERM2_CTL Register On Processors with CPUID
Family/Model/Stepping Signature Encoded as 0x69n or 0x6Dn . . . . . . . . . . . . . . . .13-8
Figure 13-4. MSR_THERM2_CTL Register for Supporting TM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
Figure 13-5. IA32_THERM_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9
Figure 13-6. IA32_THERM_INTERRUPT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Figure 13-7. IA32_CLOCK_MODULATION MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Figure 13-8. IA32_THERM_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Figure 13-9. IA32_THERM_INTERRUPT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
Figure 14-1. Machine-Check MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2
Figure 14-2. IA32_MCG_CAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3
Figure 14-3. IA32_MCG_STATUS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
Figure 14-4. IA32_MCi_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-5
Figure 14-5. IA32_MCi_STATUS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-6
Figure 14-6. IA32_MCi_ADDR MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Figure 15-1. Real-Address Mode Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-4
Figure 15-2. Interrupt Vector Table in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7
Figure 15-3. Entering and Leaving Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Figure 15-4. Privilege Level 0 Stack After Interrupt or
Exception in Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
Figure 15-5. Software Interrupt Redirection Bit Map in TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27
Figure 16-1. Stack after Far 16- and 32-Bit Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6
Figure 17-1. I/O Map Base Address Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34
Figure 18-1. Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3
Figure 18-2. DR6/DR7 Layout on Processors Supporting Intel 64 Technology . . . . . . . . . . . . . . .18-8
Figure 18-3. IA32_DEBUGCTL MSR for Processors based on Intel Core
microarchitecture . . 18-15
Figure 18-4. LBR MSR Layout for Processors Based on Intel Core Microarchitecture . . . . . . . 18-16
Figure 18-5. MSR_LASTBRANCH_TOS MSR Layout for the Pentium 4 and
Intel Xeon Processor Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
Figure 18-6. MSR_DEBUGCTLA MSR for Pentium 4 and Intel Xeon Processors. . . . . . . . . . . . . 18-22