Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-21
MULTIPLE-PROCESSOR MANAGEMENT
14. Performs the following operation to set up the BSP to detect the presence of APs
in the system and the number of processors:
— Sets the value of the COUNT variable to 1.
— Starts a timer (set for an approximate interval of 100 milliseconds). In the AP
BIOS initialization code, the AP will increment the COUNT variable to indicate
its presence. When the timer expires, the BSP checks the value of the COUNT
variable. If the timer expires and the COUNT variable has not been incre-
mented, no APs are present or some error has occurred.
15. Broadcasts an INIT-SIPI-SIPI IPI sequence to the APs to wake them up and
initialize them:
MOV ESI, ICR_LOW; Load address of ICR low dword into ESI.
MOV EAX, 000C4500H; Load ICR encoding for broadcast INIT IPI
; to all APs into EAX.
MOV [ESI], EAX; Broadcast INIT IPI to all APs
; 10-millisecond delay loop.
MOV EAX, 000C46XXH; Load ICR encoding for broadcast SIPI IP
; to all APs into EAX, where xx is the vector computed in step 10.
MOV [ESI], EAX; Broadcast SIPI IPI to all APs
; 200-microsecond delay loop
MOV [ESI], EAX; Broadcast second SIPI IPI to all APs
; 200-microsecond delay loop
Step 15:
MOV EAX, 000C46XXH; Load ICR encoding from broadcast SIPI IP
; to all APs into EAX where xx is the vector computed in step 8.
16. Waits for the timer interrupt.
17. Reads and evaluates the COUNT variable and establishes a processor count.
18. If necessary, reconfigures the APIC and continues with the remaining system
diagnostics as appropriate.
7.5.4.2 Typical AP Initialization Sequence
When an AP receives the SIPI, it begins executing BIOS AP initialization code at the
vector encoded in the SIPI. The AP initialization code typically performs the following
operations:
1. Waits on the BIOS initialization Lock Semaphore. When control of the
semaphore is attained, initialization continues.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs (using the same mapping that was used for the BSP).
4. Enables the cache.