Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-25
MULTIPLE-PROCESSOR MANAGEMENT
The CPUID feature flag may indicate support for hardware multi-threading when only
one logical processor available in the package. In this case, the decimal value repre-
sented by bits 16 through 23 in the EBX register will have a value of 1.
Software should note that the number of logical processors enabled by system soft-
ware may be less than the value of “logical processors per package”. Similarly, the
number of cores enabled by system software may be less than the value of “cores per
package”.
7.7.1 Initializing Processors
Supporting Hyper-Threading Technology
The initialization process for an MP system that contains processors supporting
Hyper-Threading Technology is the same as for conventional MP systems (see
Section 7.5, “Multiple-Processor (MP) Initialization”). One logical processor in the
system is selected as the BSP and other processors (or logical processors) are desig-
nated as APs. The initialization process is identical to that described in Section 7.5.3,
“MP Initialization Protocol Algorithm for Intel Xeon Processors,” and Section 7.5.4,
“MP Initialization Example.”
During initialization, each logical processor is assigned an APIC ID that is stored in
the local APIC ID register for each logical processor. If two or more processors
supporting Hyper-Threading Technology are present, each logical processor on the
system bus is assigned a unique ID (see Section 7.10.2, “Identifying Logical Proces-
sors in an MP System”). Once logical processors have APIC IDs, software communi-
cates with them by sending APIC IPI messages.
7.7.2 Initializing Dual-Core Processors
The initialization process for an MP system that contains dual-core Intel 64 or IA-32
processors is the same as for conventional MP systems (see Section 7.5, “Multiple-
Processor (MP) Initialization”). A logical processor in one core is selected as the BSP;
other logical processors are designated as APs.
During initialization, each logical processor is assigned an APIC ID. Once logical
processors have APIC IDs, software may communicate with them by sending APIC
IPI messages.