Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-27
MULTIPLE-PROCESSOR MANAGEMENT
7.8 INTE L
®
HYPER-THREADING TECHNOLOGY
ARCHITECTURE
Figure 7-4 shows a generalized view of an Intel processor supporting Hyper-
Threading Technology, using the original Intel Xeon processor MP as an example.
This implementation of the Hyper-Threading Technology consists of two logical
processors (each represented by a separate architectural state) which share the
processor’s execution engine and the bus interface. Each logical processor also has
its own advanced programmable interrupt controller (APIC).
Figure 7-3. Local APICs and I/O APIC in MP System Supporting HT Technology
I/O APIC
External
Interrupts
System Chip Set
Bridge
PCI
Interrupt Messages
Local APIC
Logical
Processor 0
Local APIC
Logical
Processor 1
Hyper-Threading Technology
Intel Processor with
Bus Interface
Processor Core
IPIs
Interrupt
Messages
Local APIC
Logical
Processor 0
Local APIC
Logical
Processor 1
Hyper-Threading Technology
Intel Processor with
Bus Interface
Processor Core
IPIs
Interrupt
Messages