Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-29
MULTIPLE-PROCESSOR MANAGEMENT
• Machine check global status (IA32_MCG_STATUS) and machine check capability
(IA32_MCG_CAP) MSRs
• Thermal clock modulation and ACPI Power management control MSRs
• Time stamp counter MSRs
• Most of the other MSR registers, including the page attribute table (PAT). See the
exceptions below.
• Local APIC registers.
• Additional general purpose registers (R8-R15), XMM registers (XMM8-XMM15),
control register, IA32_EFER on Intel 64 processors.
The following features are shared by logical processors:
• IA32_MISC_ENABLE MSR (MSR address 1A0H)
• Memory type range registers (MTRRs)
Whether the following features are shared or duplicated is implementation-specific:
• Machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS and
IA32_MCG_CAP MSRs)
• Performance monitoring control and counter MSRs
7.8.2 APIC Functionality
When a processor supporting Hyper-Threading Technology support is initialized, each
logical processor is assigned a local APIC ID (see Table 8-1). The local APIC ID serves
as an ID for the logical processor and is stored in the logical processor’s APIC ID
register. If two or more IA-32 processors supporting Hyper-Threading Technology are
present in a dual processor (DP) or MP system, each logical processor on the system
bus is assigned a unique local APIC ID (see Section 7.10.2, “Identifying Logical
Processors in an MP System”).
Software communicates with local processors using the APIC’s interprocessor inter-
rupt (IPI) messaging facility. Setup and programming for APICs is identical in proces-
sors that support and do not support Intel Hyper-Threading Technology. See Chapter
8, “Advanced Programmable Interrupt Controller (APIC),” for a detailed discussion.
7.8.3 Memory Type Range Registers (MTRR)
MTRRs in a processor supporting Hyper-Threading Technology are shared by logical
processors. When one logical processor updates the setting of the MTRRs, settings
are automatically shared with the other logical processors in the same physical
package.
The architectures require that all MP systems based on Intel 64 and IA-32 processors
(this includes logical processors) must use an identical MTRR memory map. This
gives software a consistent view of memory, independent of the processor on which