Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

CONTENTS
xxx Vol. 3A
PAGE
Figure 18-7. LBR MSR Branch Record Layout for the Pentium 4 and Intel Xeon
Processor Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-23
Figure 18-8. IA32_DEBUGCTL MSR for Intel Core Solo and Intel Core Duo Processors . . . . . . 18-31
Figure 18-9. LBR Branch Record Layout for the Intel Core Solo and
Intel
Core Duo Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-32
Figure 18-10. MSR_DEBUGCTLB MSR for Pentium M Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33
Figure 18-11. LBR Branch Record Layout for the Pentium M Processor . . . . . . . . . . . . . . . . . . . . .18-34
Figure 18-12. DEBUGCTLMSR Register (P6 Family Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35
Figure 18-13. Layout of IA32_PERFEVTSELx MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42
Figure 18-14. Layout of MSR_PERF_FIXED_CTR_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49
Figure 18-15. Layout of MSR_PERF_GLOBAL_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50
Figure 18-16. Layout of MSR_PERF_GLOBAL_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-51
Figure 18-17. Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-51
Figure 18-18. Event Selection Control Register (ESCR) for Pentium 4 and
Intel Xeon Processors without HT Technology Support . . . . . . . . . . . . . . . . . . . . . . 18-60
Figure 18-19. Performance Counter (Pentium 4 and Intel Xeon Processors). . . . . . . . . . . . . . . . .18-62
Figure 18-20. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63
Figure 18-21. DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66
Figure 18-22. 32-bit Branch Trace Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67
Figure 18-23. PEBS Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-68
Figure 18-24. IA-32e Mode DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-69
Figure 18-25. 64-bit Branch Trace Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70
Figure 18-26. 64-bit PEBS Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70
Figure 18-27. Effects of Edge Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-75
Figure 18-28. Event Selection Control Register (ESCR) for the Pentium 4 Processor,
Intel Xeon Processor and Intel Xeon Processor MP Supporting
Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-86
Figure 18-29. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-88
Figure 18-30. Block Diagram of 64-bit Intel Xeon Processor MP with 8-MByte L3 . . . . . . . . . . .18-94
Figure 18-31. MSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH . . . . . . . . . . . . . . . . . . . . . . . .18-95
Figure 18-32. MSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFH . . . . . . . . . . . . . . . . . . . . . . . . 18-96
Figure 18-33. MSR_EFSB_DRDYx, Addresses: 107D0H and 107D1H . . . . . . . . . . . . . . . . . . . . . . .18-97
Figure 18-34. MSR_IFSB_CTL6, Address: 107D2H; MSR_IFSB_CNTR7, Address: 107D3H . . . . 18-98
Figure 18-35. PerfEvtSel0 and PerfEvtSel1 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-100
Figure 18-36. CESR MSR (Pentium Processor Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-104
Figure 19-1. Interaction of a Virtual-Machine Monitor and Guests . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Figure 19-2. CPUID Extended Feature Information ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
Figure 24-1. SMRAM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
Figure 24-2. SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
Figure 24-3. Auto HALT Restart Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-19
Figure 24-4. SMBASE Relocation Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-20
Figure 24-5. I/O Instruction Restart Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-21
Figure 25-1. VMX Transitions and States of VMCS in a Logical Processor . . . . . . . . . . . . . . . . . . . 25-4
Figure 26-1. Virtual TLB Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
Figure 27-1. Host External Interrupts and Guest Virtual Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 27-5
Figure C-1. MP System With Multiple Pentium III Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3