Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-31
MULTIPLE-PROCESSOR MANAGEMENT
7.8.7 Performance Monitoring Counters
Performance counters and their companion control MSRs are shared between the
logical processors within the physical processor. As a result, software must manage
the use of these resources. The performance counter interrupts, events, and precise
event monitoring support can be set up and allocated on a per thread (per logical
processor) basis.
See Section 18.16, “Performance Monitoring and Hyper-Threading Technology,” for a
discussion of performance monitoring in the Intel Xeon processor MP.
7.8.8 IA32_MISC_ENABLE MSR
The IA32_MISC_ENABLE MSR (MSR address 1A0H) is shared between the logical
processors in an IA-32 processor supporting Hyper-Threading Technology. Thus the
architectural features that this register controls are set the same for all the logical
processors in the same physical package.
7.8.9 Memory Ordering
The logical processors in an Intel 64 or IA-32 processor supporting Hyper-Threading
Technology obey the same rules for memory ordering as Intel 64 or IA-32 processors
without HT Technology (see Section 7.2, “Memory Ordering”). Each logical processor
uses a processor-ordered memory model that can be further defined as “write-
ordered with store buffer forwarding.” All mechanisms for strengthening or weak-
ening the memory ordering model to handle special programming situations apply to
each logical processor.
7.8.10 Serializing Instructions
As a general rule, when a logical processor in a processor supporting Hyper-
Threading Technology executes a serializing instruction, only that logical processor is
affected by the operation. An exception to this rule is the execution of the WBINVD,
INVD, and WRMSR instructions; and the MOV CR instruction when the state of the CD
flag in control register CR0 is modified. Here, both logical processors are serialized.
7.8.11 MICROCODE UPDATE Resources
In an Intel processor supporting Hyper-Threading Technology, the microcode update
facilities are shared between the logical processors; either logical processor can
initiate an update. Each logical processor has its own BIOS signature MSR
(IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical processor performs an
update for the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical
processors are updated with identical information. If logical processors initiate an