Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-33
MULTIPLE-PROCESSOR MANAGEMENT
• CD flag in control register CR0 — Each logical processor has its own CR0
control register, and thus its own CD flag in CR0. The CD flags for the two logical
processors are ORed together, such that when any logical processor sets its CD
flag, the entire cache is nominally disabled.
7.8.13.2 Processor Translation Lookaside Buffers (TLBs)
In processors supporting Hyper-Threading Technology, data cache TLBs are shared.
The instruction cache TLB is duplicated in each logical processor.
Entries in the TLBs are tagged with an ID that indicates the logical processor that
initiated the translation. This tag applies even for translations that are marked global
using the page global feature for memory paging.
When a logical processor performs a TLB invalidation operation, only the TLB entries
that are tagged for that logical processor are flushed. This protocol applies to all TLB
invalidation operations, including writes to control registers CR3 and CR4 and uses of
the INVLPG instruction.
7.8.13.3 Thermal Monitor
In a processor that supports Hyper-Threading Technology, logical processors share
the catastrophic shutdown detector and the automatic thermal monitoring mecha-
nism (see Section 13.4, “Thermal Monitoring and Protection”). Sharing results in the
following behavior:
• If the processor’s core temperature rises above the preset catastrophic shutdown
temperature, the processor core halts execution, which causes both logical
processors to stop execution.
• When the processor’s core temperature rises above the preset automatic thermal
monitor trip temperature, the clock speed of the processor core is automatically
modulated, which effects the execution speed of both logical processors.
For software controlled clock modulation, each logical processor has its own
IA32_CLOCK_MODULATION MSR, allowing clock modulation to be enabled or
disabled on a logical processor basis. Typically, if software controlled clock modula-
tion is going to be used, the feature must be enabled for all the logical processors
within a physical processor and the modulation duty cycle must be set to the same
value for each logical processor. If the duty cycle values differ between the logical
processors, the processor clock will be modulated at the highest duty cycle selected.
7.8.13.4 External Signal Compatibility
This section describes the constraints on external signals received through the pins
of a processor supporting Hyper-Threading Technology and how these signals are
shared between its logical processors.
• STPCLK# — A single STPCLK# pin is provided on the physical package of the
Intel Xeon processor MP. External control logic uses this pin for power