Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-34 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
management within the system. When the STPCLK# signal is asserted, the
processor core transitions to the stop-grant state, where instruction execution is
halted but the processor core continues to respond to snoop transactions.
Regardless of whether the logical processors are active or halted when the
STPCLK# signal is asserted, execution is stopped on both logical processors and
neither will respond to interrupts.
In MP systems, the STPCLK# pins on all physical processors are generally tied
together. As a result this signal affects all the logical processors within the system
simultaneously.
• LINT0 and LINT1 pins — A processor supporting Hyper-Threading Technology
has only one set of LINT0 and LINT1 pins, which are shared between the logical
processors. When one of these pins is asserted, both logical processors respond
unless the pin has been masked in the APIC local vector tables for one or both of
the logical processors.
Typically in MP systems, the LINT0 and LINT1 pins are not used to deliver
interrupts to the logical processors. Instead all interrupts are delivered to the
local processors through the I/O APIC.
• A20M# pin — On an IA-32 processor, the A20M# pin is typically provided for
compatibility with the Intel 286 processor. Asserting this pin causes bit 20 of the
physical address to be masked (forced to zero) for all external bus memory
accesses. Processors supporting Hyper-Threading Technology provide one
A20M# pin, which affects the operation of both logical processors within the
physical processor.
7.9 DUAL-CORE ARCHITECTURE
This section describes the architecture of dual-core Intel 64 and IA-32 processors.
The discussion is applicable to the Intel Pentium processor Extreme Edition,
Pentium D, Intel Core Duo, Intel Core 2 Duo, and Dual-core Intel Xeon processor.
Features vary across different microarchitectures and are detectable using CPUID.
In general, each processor core has dedicated microarchitectural resources identical
to a single-processor implementation of the underlying microarchitecture without
hardware multi-threading capability. Each logical processor in a dual-core processor
(whether supporting Hyper-Threading Technology or not) has its own APIC function-
ality, PAT, machine check architecture, debug registers and extensions. Each logical
processor handles serialization instructions or self-modifying code on its own.
Memory order is handled the same way as in Hyper-Threading Technology.
The topology of the cache hierarchy (with respect to whether a given cache level is
shared by one or more processor cores or by all logical processors in the physical
package) depends on the processor implementation. Software must use the deter-
ministic cache parameter leaf of CPUID instruction to discover the cache-sharing
topology between the logical processors in a multi-threading environment.