Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-35

MULTIPLE-PROCESSOR MANAGEMENT

7.9.1 Logical Processor Support

The topological composition of processor cores and logical processors in a multi-core

processor can be discovered using CPUID. Within each processor core, one or more

logical processors may be available.

System software must follow the requirement MP initialization sequences (see

Section 7.5, “Multiple-Processor (MP) Initialization”) to recognize and enable logical

processors. At runtime, software can enumerate those logical processors enabled by

system software to identify the topological relationships between these logical

processors. (See Section 7.10.4, “Identifying Topological Relationships in a MP

System”).

7.9.2 Memory Type Range Registers (MTRR)

MTRR is shared between two logical processors sharing a processor core if the phys-

ical processor supports Hyper-Threading Technology. MTRR is not shared between

logical processors located in different cores or different physical packages.

The Intel 64 and IA-32 architectures require that all logical processors in an MP

system use an identical MTRR memory map. This gives software a consistent view of

memory, independent of the processor on which it is running.

See Section 10.11, “Memory Type Range Registers (MTRRs).”

7.9.3 Performance Monitoring Counters

Performance counters and their companion control MSRs are shared between two

logical processors sharing a processor core if the processor core supports Hyper-

Threading Technology. They are not shared between logical processors in different

cores or different physical packages. As a result, software must manage the use of

these resources, based on the topology of performance monitoring resources. Perfor-

mance counter interrupts, events, and precise event monitoring support can be set

up and allocated on a per thread (per logical processor) basis.

See Section 18.16, “Performance Monitoring and Hyper-Threading Technology.”

7.9.4 IA32_MISC_ENABLE MSR

The IA32_MISC_ENABLE MSR (MSR address 1A0H) is shared between two logical

processors sharing a processor core if the processor core supports Hyper-Threading

Technology. The MSR is not shared between logical processors in different cores or

different physical packages. This means that the architectural features that this