Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

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MULTIPLE-PROCESSOR MANAGEMENT
7.9.5 MICROCODE UPDATE Resources
Microcode update facilities are shared between two logical processors sharing a
processor core if the physical package supports Hyper-Threading Technology. They
are not shared between logical processors in different cores or different physical
packages. Either logical processor that has access to the microcode update facility
can initiate an update.
Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR
address 8BH). When a logical processor performs an update for the physical
processor, the IA32_BIOS_SIGN_ID MSRs for resident logical processors are
updated with identical information. If logical processors initiate an update simulta-
neously, the processor core provides the synchronization needed to ensure that only
one update is performed at a time.
7.10 PROGRAMMING CONSIDERATIONS FOR HARDWARE
MULTI-THREADING CAPABLE PROCESSORS
In a multi-threading environment, there may be certain hardware resources that are
physically shared at some level of the hardware topology. In the multi-processor
systems, typically bus and memory sub-systems are physically shared between
multiple sockets. Within a hardware multi-threading capable processors, certain
resources are provided for each processor core, while other resources may be
provided for each logical processors (see Section 7.8, “Intel
®
Hyper-Threading Tech-
nology Architecture,” and Section 7.9, “Dual-Core Architecture”).
From a software programming perspective, control transfer of processor operation is
managed at the granularity of logical processor (operating systems dispatch a
runnable task by allocating an available logical processor on the platform). To
manage the topology of shared resources in a multi-threading environment, it is
useful for software to understand and manage resources that may be shared by more
than one logical processors. This can be facilitated by mapping several levels of hier-
archical labels to the initial APIC_ID of each logical processor to identify the topology
of shared resources.
7.10.1 Hierarchical Mapping of Shared Resources
The initial APIC_ID value associated with each logical processor in a multi-processor
system is unique (see Section 7.7, “Detecting Hardware Multi-Threading Support and
Topology”). This 8-bit value can be decomposed into sub-fields, where each sub-field
corresponds a hierarchical level of the topological mapping of hardware resources.