Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-38 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
context (See Example 7-3) is limited to the number of logical processors enabled at
runtime by the OS boot process.
Table 7-1 shows the APIC IDs that are initially reported for logical processors in a
system with four Intel Xeon MP processors that support Hyper-Threading Technology
(a total of 8 logical processors, each physical package has two processor cores and
supports Hyper-Threading Technology). Of the two logical processors within a Intel
Xeon processor MP, logical processor 0 is designated the primary logical processor
and logical processor 1 as the secondary logical processor.
Figure 7-6. Topological Relationships between Hierarchical IDs in a Hypothetical MP
Platform
Table 7-1. Initial APIC IDs for the Logical Processors in a System that has Four Intel
Xeon MP Processors Supporting Hyper-Threading Technology
1
Initial APIC ID of Logical
Processor
Package ID Core ID SMT ID
0H 0H 0H 0H
1H 0H 0H 1H
2H 1H 0H 0H
3H 1H 0H 1H
4H 2H 0H 0H
5H 2H 0H 1H
6H 3H 0H 0H
7H 3H 0H 1H
NOTE:
1. Because information on the number of processor cores in a physical package was not available
in early single-core processors supporting Hyper-Threading Technology, the core ID can be
treated as 0.
Package 0
Core 0
T0
T1
Core1
T0
T1
Package 1
Core 0
T0
T1
Core1
T0
T1
SMT_ID
Core ID
Package ID