Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-39
MULTIPLE-PROCESSOR MANAGEMENT
Table 7-2 shows the initial APIC IDs for a hypothetical situation with a dual processor
system. Each physical package providing two processor cores, and each processor
core also supporting Hyper-Threading Technology.
7.10.3 Algorithm for Three-Level Mappings of APIC_ID
Software can gather the initial APIC_IDs for each logical processor supported by the
operating system at runtime
1
and extract identifiers corresponding to the three
levels of sharing topology (package, core, and SMT). The algorithms below focus on
a non-clustered MP system for simplicity. They do not assume initial APIC_IDs are
contiguous or that all logical processors on the platform are enabled.
Intel supports multi-threading systems where all physical processors report identical
values in CPUID.1:EBX[23:16]), CPUID.4
2
:EAX[31:26], and CPUID.4
3
:EAX[25:14].
The algorithms below assume the target system has symmetry across physical
package boundaries with respect to the number of logical processors per package,
number of cores per package, and cache topology within a package.
Table 7-2. Initial APIC IDs for the Logical Processors in a System that has Two
Physical Processors Supporting Dual-Core and Hyper-Threading Technology
Initial APIC ID of a Logical
Processor
Package ID Core ID SMT ID
0H 0H 0H 0H
1H 0H 0H 1H
2H 0H 1H 0H
3H 0H 1H 1H
4H 1H 0H 0H
5H 1H 0H 1H
6H 1H 1H 0H
7H 1H 1H 1H
1. As noted in Section 7.7 and Section 7.10.2, the number of logical processors supported by the
OS at runtime may be less than the total number logical processors available in the platform
hardware.
2. Maximum number of cores per physical processor is obtained by executing CPUID with EAX=4
and a valid ECX index, The ECX index start at 0.
3. Maximum number of cores sharing the target cache level is obtained by executing CPUID with
EAX = 4 and the ECX index corresponding to the target cache level.