Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A xxxi
CONTENTS
PAGE
TABLES
Table 2-1. Action Taken By x87 FPU Instructions for Different Combinations of
EM, MP, and TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21
Table 2-2. Summary of System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26
Table 3-1. Code- and Data-Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
Table 3-2. System-Segment and Gate-Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
Table 3-3. Page Sizes and Physical Address Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25
Table 3-4. Reserved Bit Checking When Execute Disable Bit is Disabled . . . . . . . . . . . . . . . . . . .3-48
Table 3-5. Reserved Bit Checking When Execute Disable Bit is Enabled . . . . . . . . . . . . . . . . . . .3-49
Table 4-1. Privilege Check Rules for Call Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Table 4-2. 64-Bit-Mode Stack Layout After CALLF with CPL Change . . . . . . . . . . . . . . . . . . . . . .4-28
Table 4-3. Combined Page-Directory and Page-Table Protection. . . . . . . . . . . . . . . . . . . . . . . . . .4-42
Table 4-4. Page Sizes and Physical Address Sizes Supported by Execute-Disable
Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-43
Table 4-5. Extended Feature Enable MSR (IA32_EFER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-44
Table 4-6. IA-32e Mode Page Level Protection Matrix with Execute-Disable
Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-44
Table 4-7. Legacy PAE-Enabled 4-KByte Page Level Protection Matrix with
Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-45
Table 4-8. Legacy PAE-Enabled 2-MByte Page Level Protection with Execute-Disable
Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-45
Table 4-9. IA-32e Mode Page Level Protection Matrix with Execute-Disable
Bit Capability Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-46
Table 4-10. Reserved Bit Checking WIth Execute-Disable Bit Capability Not Enabled . . . . . . . .4-47
Table 5-1. Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Table 5-2. Priority Among Simultaneous Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . .5-11
Table 5-3. Debug Exception Conditions and Corresponding Exception Classes . . . . . . . . . . . . .5-30
Table 5-4. Interrupt and Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-39
Table 5-5. Conditions for Generating a Double Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
Table 5-6. Invalid TSS Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-43
Table 5-7. Alignment Requirements by Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-60
Table 5-8. SIMD Floating-Point Exceptions Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-65
Table 6-1. Exception Conditions Checked During a Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
Table 6-2. Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field,
and TS Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17
Table 7-1. Initial APIC IDs for the Logical Processors in a System that has
Four Intel Xeon MP Processors Supporting Hyper-Threading Technology . . . . . . .7-38
Table 7-2. Initial APIC IDs for the Logical Processors in a System that has
Two Physical Processors Supporting Dual-Core and Hyper-Threading
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-39
Table 8-1. Local APIC Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Table 8-2. ESR Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20
Table 8-3. Valid Combinations for the Pentium 4 and Intel Xeon Processors’
Local xAPIC Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27
Table 8-4. Valid Combinations for the P6 Family Processors’
Local APIC Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-28
Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT . . . . . . . . . . . . . . . . . . . . . 9-3
Table 9-2. Recommended Settings of EM and MP Flags on IA-32 Processors . . . . . . . . . . . . . . . 9-7
Table 9-3. Software Emulation Settings of EM, MP, and NE Flags . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Table 9-4. Main Initialization Steps in STARTUP.ASM Source Listing . . . . . . . . . . . . . . . . . . . . . .9-21
Table 9-5. Relationship Between BLD Item and ASM Source File . . . . . . . . . . . . . . . . . . . . . . . . . .9-36