Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-48 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
7.11.1 HLT Instruction
The HLT instruction stops the execution of the logical processor on which it is
executed and places it in a halted state until further notice (see the description of the
HLT instruction in Chapter 3 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A). When a logical processor is halted, active logical
processors continue to have full access to the shared resources within the physical
package. Here shared resources that were being used by the halted logical processor
become available to active logical processors, allowing them to execute at greater
efficiency. When the halted logical processor resumes execution, shared resources
are again shared among all active logical processors. (See Section 7.11.6.3, “Halt
Idle Logical Processors,” for more information about using the HLT instruction with
processors supporting Hyper-Threading Technology.)
7.11.2 PAUSE Instruction
The PAUSE instruction can improves the performance of processors supporting
Hyper-Threading Technology when executing “spin-wait loops” and other routines
where one thread is accessing a shared lock or semaphore in a tight polling loop.
When executing a spin-wait loop, the processor can suffer a severe performance
penalty when exiting the loop because it detects a possible memory order violation
and flushes the core processor’s pipeline. The PAUSE instruction provides a hint to
the processor that the code sequence is a spin-wait loop. The processor uses this hint
to avoid the memory order violation and prevent the pipeline flush. In addition, the
PAUSE instruction de-pipelines the spin-wait loop to prevent it from consuming
execution resources excessively. (See Section 7.11.6.1, “Use the PAUSE Instruction
in Spin-Wait Loops,” for more information about using the PAUSE instruction with
IA-32 processors supporting Hyper-Threading Technology.)
7.11.3 Detecting Support MONITOR/MWAIT Instruction
Streaming SIMD Extensions 3 introduced two instructions (MONITOR and MWAIT) to
help multithreaded software improve thread synchronization. In the initial imple-
mentation, MONITOR and MWAIT are available to software at ring 0. The instructions
are conditionally available at levels greater than 0. Use the following steps to detect
the availability of MONITOR and MWAIT:
• Use CPUID to query the MONITOR bit (CPUID.1.ECX[3] = 1).
• If CPUID indicates support, execute MONITOR inside a TRY/EXCEPT exception
handler and trap for an exception. If an exception occurs, MONITOR and MWAIT
are not supported at a privilege level greater than 0. See Example 7-4.