Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-50 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
(due to a variety of events, including a store to the monitored memory region). If
upon execution of MWAIT, monitor hardware is in a triggered state: MWAIT behaves
as a NOP and execution continues at the next instruction in the execution stream.
The state of monitor hardware is not architecturally visible except through the
behavior of MWAIT.
Multiple events other than a write to the triggering address range can cause a
processor that executed MWAIT to wake up. These include events that would lead to
voluntary or involuntary context switches, such as:
• External interrupts, including NMI, SMI, INIT, BINIT, MCERR, A20M#
• Faults, Aborts (including Machine Check)
• Architectural TLB invalidations including writes to CR0, CR3, CR4 and certain MSR
writes; execution of LMSW (occurring prior to issuing MWAIT but after setting the
monitor)
• Voluntary transitions due to fast system call and far calls (occurring prior to
issuing MWAIT but after setting the monitor)
Power management related events (such as Thermal Monitor 2 or chipset driven
STPCLK# assertion) will not cause the monitor event pending flag to be cleared.
Faults will not cause the monitor event pending flag to be cleared.
Software should not allow for voluntary context switches in between
MONITOR/MWAIT in the instruction flow. Note that execution of MWAIT does not re-
arm the monitor hardware. This means that MONITOR/MWAIT need to be executed in
a loop. Also note that exits from the MWAIT state could be due to a condition other
than a write to the triggering address; software should explicitly check the triggering
data location to determine if the write occurred. Software should also check the value
of the triggering address following the execution of the monitor instruction (and prior
to the execution of the MWAIT instruction). This check is to identify any writes to the
triggering address that occurred during the course of MONITOR execution.
The address range provided to the MONITOR instruction must be of write-back
caching type. Only write-back memory type stores to the monitored address range
will trigger the monitor hardware. If the address range is not in memory of write-
back type, the address monitor hardware may not be set up properly or the monitor
hardware may not be armed. Software is also responsible for ensuring that
• Writes that are not intended to cause the exit of a busy loop do not write to a
location within the address region being monitored by the monitor hardware,
• Writes intended to cause the exit of a busy loop are written to locations within the
monitored address region.
Not doing so will lead to more false wakeups (an exit from the MWAIT state not due
to a write to the intended data location). These have negative performance implica-
tions. It might be necessary for software to use padding to prevent false wakeups.
CPUID provides a mechanism for determining the size data locations for monitoring
as well as a mechanism for determining the size of a the pad.