Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 7-51
MULTIPLE-PROCESSOR MANAGEMENT
7.11.5 Monitor/Mwait Address Range Determination
To use the MONITOR/MWAIT instructions, software should know the length of the
region monitored by the MONITOR/MWAIT instructions and the size of the coherence
line size for cache-snoop traffic in a multiprocessor system. This information can be
queried using the CPUID monitor leaf function (EAX = 05H). You will need the
smallest and largest monitor line size:
• To avoid missed wake-ups: make sure that the data structure used to monitor
writes fits within the smallest monitor line-size. Otherwise, the processor may
not wake up after a write intended to trigger an exit from MWAIT.
• To avoid false wake-ups; use the largest monitor line size to pad the data
structure used to monitor writes. Software must make sure that beyond the data
structure, no unrelated data variable exists in the triggering area for MWAIT. A
pad may be needed to avoid this situation.
These above two values bear no relationship to cache line size in the system and soft-
ware should not make any assumptions to that effect. Within a single-cluster system,
the two parameters should default to be the same (the size of the monitor triggering
area is the same as the system coherence line size).
Based on the monitor line sizes returned by the CPUID, the OS should dynamically
allocate structures with appropriate padding. If static data structures must be used
by an OS, attempt to adapt the data structure and use a dynamically allocated data
buffer for thread synchronization. When the latter technique is not possible, consider
not using MONITOR/MWAIT when using static data structures.
To set up the data structure correctly for MONITOR/MWAIT on multi-clustered
systems: interaction between processors, chipsets, and the BIOS is required (system
coherence line size may depend on the chipset used in the system; the size could be
different from the processor’s monitor triggering area). The BIOS is responsible to
set the correct value for system coherence line size using the
IA32_MONITOR_FILTER_LINE_SIZE MSR. Depending on the relative magnitude of
the size of the monitor triggering area versus the value written into the
IA32_MONITOR_FILTER_LINE_SIZE MSR, the smaller of the parameters will be
reported as the Smallest Monitor Line Size. The larger of the parameters will be
reported as the Largest Monitor Line Size.
7.11.6 Required Operating System Support
This section describes changes that must be made to an operating system to run on
processors supporting Hyper-Threading Technology. It also describes optimizations
that can help an operating system make more efficient use of the logical processors
sharing execution resources. The required changes and suggested optimizations are
representative of the types of modifications that appear in Windows* XP and Linux*
kernel 2.4.0 operating systems for Intel processors supporting Hyper-Threading
Technology. Additional optimizations for processors supporting Hyper-Threading
Technology are described in the Intel® 64 and IA-32 Architectures Optimization
Reference Manual.